The invention is generally related to the design and testing of integrated circuits. More specifically, the invention is generally related to debugging computer-aided designed integrated circuits incorporating modular circuit components.
As semiconductor fabrication technology advances, designers of integrated circuits are able to integrate more and more functions into a single integrated circuit device, or chip. Whereas chips once included only hundreds or thousands of logic gates, advances in fabrication technology have resulted the ability to place millions of logic gates on a single chip.
Given the increasing complexity of integrated circuit designs, however, the design and testing of such designs has become increasingly difficult. To facilitate these operations, various electronic design automation (EDA) software programs, also referred to as xe2x80x9ctoolsxe2x80x9d, have been developed to permit a developer to define an integrated circuit design in software at a relatively higher conceptual level, and then perform operations such as synthesizing the physical layout of the integrated circuit design, testing the integrating circuit design, etc., performed with the assistance of a computer. Manufacturing physical chips is often an expensive endeavor, particularly if a particular chip design has to be reworked to correct flaws in the design. As a result, development costs are often minimized by maximizing the amount of design and testing performed in software.
Integrated circuit design has paralleled many of the concepts embodied in object-oriented software design, where commonly-used circuit components are compartmentalized into objects, referred to herein as xe2x80x9ccircuit blocksxe2x80x9d, that have been developed, tested and validated for reuse in multiple designs. Design of an integrated circuit can therefore proceed by assembling multiple circuit blocks together to the extent possible, and then developing any xe2x80x9cglue logicxe2x80x9d necessary to interface the circuit blocks together into an operative design. The functionality encapsulated within circuit blocks has also increased over time, i.e., from relatively simple circuit blocks that represented simple logical components such as multiplexers and registers, to more complex functional components such as bus interfaces, memory arrays and interfaces, test circuits, etc. Some circuit blocks are also developed to interface over standardized interfaces, thereby further minimizing the amount of additional custom circuitry required to implement such blocks in custom designs.
By utilizing an assemblage of pre-existing circuit blocks, development costs and time can be substantially reduced, as a developer is often required to generate only minimal customized circuitry to interface the pre-existing blocks, rather than having to recreate the functionality of all of the blocks from scratch. A circuit designer is also often able to rely on the previous validation and testing performed on pre-existing blocks to eliminate the need to test all of the internal aspects of each and every circuit block in a design.
Circuit block designs have also advanced to the point where complex, programmable processing units such as microprocessors and programmable digital signal processors may be encapsulated into pre-designed and tested xe2x80x9cprogrammable coresxe2x80x9d suitable for combining with interface circuitry and other logic to define a custom processing integrated circuit design. Typically, such programmable cores support standardized interfaces such as communication busses, such that any circuit block that is capable of interfacing with such a standardized interface can be integrated with the programmable cores with little or no additional circuitry.
Circuit blocks such as programmable cores typically incorporate both functional information, which defines how the resulting circuit component will respond to particular inputs, as well as synthesis information (e.g., netlists), from which the physical implementation of the circuit component can be synthesized. However, in certain instances, it is desirable to separate functional and synthesis information for a circuit block, particularly if it is desirable to limit third party access to the synthesis information.
For example, it may be desirable for an application specific integrated circuit (ASIC) developer and manufacturer to provide customers with functional information about programmable cores that such customers wish to use in their custom integrated circuit designs, so that the customers can verify the functional operation of the circuit blocks in the custom designs. However, given that development of programmable cores is often expensive and time consuming, it may be important from an intellectual property protection perspective for the synthesis information necessary to actually synthesize and manufacture physical chips using the programmable cores not be disclosed to the customers, for fear of those customers reusing the programmable cores in other designs without the core developer""s consent and without compensation to the developer. In addition, often a core developer licenses a standard programmable core design from another entity and customizes the programmable core for use in a particular type of application, paying royalties for each use of the customized programmable core to the owner of the standard design. Often, licensing terms prohibit the disclosure of the synthesis information to third parties, so providing such information to customers of a customized licensed programmable core design would violate the developer""s license.
In part to address these concerns, core simulation models have been developed to emulate or mimic the functional characteristics of programable cores, without providing any synthesis information that could be used to generate physical designs of the cores. Core simulation models are typically usable with a simulator program for the purpose of simulating the operational characteristics of a core, as well as to verify the proper interaction of the core with other components in a design. Programmable core models are typically useful when testing a design at various levels of simulation, including, for example, at the register transfer level (RTL) and/or the gate level.
Often, programmable core models are generated for use in a specific simulation environment, i.e., for use with a specific simulator platform. Generic core models have also been developed, which are simulator-independent, and which can be compiled for use with different simulator platforms.
Computer-aided design and testing of programmable core models, however, can be problematic with conventional simulators. Traditionally, software-based hardware simulation enables developers to analyze the states of particular nodes in a design at particular times. However, node state analysis is generally not well suited for analyzing the execution of a computer program by a programmable core, as the states of individual nodes in a programmable core may not be representative of how the programmable core handles the execution of different program instructions. Moreover, given that programmable core models model the overall function of a programmable core, some internal nodes of a programmable core model may not even be accessible to a simulator.
In this regard, testing of a programmable core or its model is more analogous to debugging computer software, as both involve the execution of program instructions. A number of tools have been developed for debugging computer software, providing features such as breakpoints, step-wise execution, traces, disassembly, etc.; however, such functionality has conventionally not be available for programmable cores used in integrated circuit designs. Likewise, debugging functionality has been supported in various hardware test benches for monitoring the operation of a physical microprocessor chip in an electronic circuit as the microprocessor chip executes a computer program. However, to date, such debugging functionality has not been readily available for assisting in the testing and simulation of a software-based programmable core.
As programmable cores and core models continue to become more complex and rely on increasingly complex embedded programs, the need for debugging-type functionality during simulation will continue to increase. Therefore, a significant need exists in the art for a manner of supporting debugging functionality for use in conjunction with simulation of a programmable core.
The invention addresses these and other problems associated with the prior art by providing an apparatus, program product and method in which an enhanced programmable core model incorporates an embedded debug monitor to provide integrated graphical debugging functionality in the model. The debug monitor supports the performance of one or more debug operations on the programmable core model during simulation thereof. In addition, the debug monitor is configured to receive a debug parameter from a user through a graphical user interface, and report a result of the debug operation to a user via the graphical user interface. Through the use of a graphical user interface, interaction with a user is greatly facilitated. Moreover, by embedding the debug monitor within the programmable core model, a completely integrated simulation and debug environment may be provided to a user, with debugging functionality similar to that available to software developers and hardware-based processor designers. As a result, validation of a model""s performance can be performed more efficiently and with less effort.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.